1. Field of the Invention
The present invention relates to the fields of emulation systems in general and, in particular, to a reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system.
2. Background Information
Emulation systems for emulating circuit design are known in the art. Typically, prior art emulation systems are formed using general purpose field programmable gate arrays (FPGA's) without integrated debugging facilities. A circuit design to be emulated is "realized" on the emulation system by compiling a "formal" description of the circuit design, and mapping the circuit design onto the logic elements (LEs) (also known as combinatorial logic blocks (CLBs)) of the FPGAs. These general purpose FPGAs, as far as their applications to emulation systems are concerned, have a number of disadvantages. First of all, the states of signals at individual nodes mapped inside of the FPGAs are not directly observable, thus the term "hidden" nodes. In order to be able to observe the states of signals at these "hidden" nodes, reconfiguration of the FPGAs, requiring an extremely time consuming recompilation, is required to bring these signals outside the FPGAs to a logic analyzer. In addition, a number of the FPGA I/Os are typically consumed in order to bring these signals to a port/node which is observable (traceable) by a test system, e.g., a logic analyzer. Furthermore, the additional signals to be routed further increase signal routing congestion. Finally, for time sensitive applications, it is difficult to know whether the signals at these "hidden" nodes were read at precisely the correct time or not, if the signals are to be read in response to the occurrence of certain events, since the signals have to be brought out of the FPGAs before the read triggering events can be detected. As the emulators have grown more complex, so too have the network of FPGAs and interconnecting traces, further exacerbating the problems above. As the time required for monitoring traces exhaustively increases with the increased complexity, the frequency at which the emulation can proceed is diminished to unacceptable levels.
Thus, what is required is a reconfigurable integrated circuit with integrated debugging facilities which facilitates access to once hidden nodes and traces while reducing the need for reconfiguration, thereby facilitating emulation at acceptable emulation frequencies. As will be described in more detail below, the present invention provides for just such a reconfigurable integrated circuit with integrated debugging facilities that achieves these and other desired results, which will be apparent to those skilled in the art from the description to follow.